PCB Design Best Practices for High-Speed Digital Circuits

Why high-speed design is different

At low frequencies a copper trace behaves like a wire: a connection with negligible character of its own. As edge rates get faster, that abstraction breaks. The trace becomes a transmission line with a characteristic impedance, and any discontinuity in that impedance reflects energy back at the source, corrupting the signal that follows.

The important insight, and the one most often missed, is that this is driven by rise time, not clock frequency. A 10 MHz clock with a 500 picosecond edge contains substantial energy well into the hundreds of megahertz. Engineers who assume they are safe because the clock is slow get caught by this constantly.

The stack-up is the foundation

Almost every high-speed problem we are asked to debug traces back to the layer stack-up, and by then it is too late to fix cheaply. Decide the stack-up before you route a single trace.

The minimum viable high-speed stack is four layers: signal, ground, power, signal. What you are buying is an uninterrupted ground plane sitting directly under your signal layer. That plane does two jobs at once. It gives every signal a low-impedance return path directly beneath it, and it sets a predictable, controllable impedance for the traces above it.

Return current is the concept to internalise. High-frequency return current does not take the shortest path back to the source; it takes the path of least inductance, which means it flows in the plane directly under the trace, mirroring it. Cut a slot in that plane, and you have forced the return current on a detour. The loop area grows, the loop becomes an antenna, and you have created both an EMI emitter and a signal integrity problem in a single stroke.

Controlled impedance

Once traces are transmission lines, their impedance must match the driver and the load, or energy reflects. The conventional targets are 50 Ω for single-ended traces and 90 to 100 Ω differential, though the correct number always comes from the interface specification you are implementing.

Impedance is set by geometry and material: trace width, the height of the dielectric between trace and reference plane, the dielectric constant of the laminate, and copper thickness. You do not guess these values. You give your target impedance to your fabricator, who will return a stack-up with the trace widths that achieve it in their process, with their material. Then you route to those widths.

Designers who pick a trace width because it looked reasonable, and only discover at fabrication that their 50 Ω line is actually 68 Ω, are the reason respins exist.

Differential pairs

Modern high-speed interfaces (USB, HDMI, Ethernet, PCIe, LVDS) are differential because differential signalling rejects common-mode noise and contains its own return path. To get those benefits, the pair must be routed as a pair.

• Match the lengths. Skew between the two halves converts differential signal into common-mode noise, which is exactly what you were trying to avoid. Serpentine the shorter trace to compensate.
• Keep the spacing constant. The differential impedance depends on the gap between the two traces. If the gap wanders, so does the impedance.
• Route them together. They should see the same reference plane, the same layer changes and the same environment for their entire journey.
• Keep other signals away. Give a differential pair generous clearance from unrelated traces, particularly clocks.

Crosstalk and the 3W rule

Adjacent traces couple into each other through their electromagnetic fields. The energy that leaks from an aggressor trace into a victim trace is crosstalk, and it is the reason two perfectly good signals can corrupt each other simply by running next to one another for too long.

The practical mitigation is spacing: keep centre-to-centre separation at least three times the trace width, which is where the 3W rule comes from. Coupling falls off quickly with distance, so a modest increase in spacing buys a large reduction in crosstalk. Apply it most rigorously to clocks, which are both the worst aggressors and, when corrupted, the most damaging victims.

Where spacing is not available, reduce the parallel run length. Crosstalk accumulates over distance, so two traces that run together for 5 mm couple far less than two that run together for 50 mm.

Vias and stubs

Every via is an impedance discontinuity. You cannot avoid them entirely, but you can avoid the worst of their effects.

The pathology worth knowing is the via stub. When a signal enters a via on layer 1 and leaves on layer 4 of a six-layer board, the remainder of the via barrel below layer 4 is still there, electrically. It is an unterminated stub, and at the frequency where that stub is a quarter wavelength it becomes a resonant trap that notches your signal out of existence.

The fixes, in increasing order of cost: route so that layer transitions use most of the via's depth; use blind or buried vias so the stub does not exist; or back-drill the stub away after fabrication. On genuinely fast interfaces, back-drilling is routine rather than exotic.

Also place ground stitching vias near any signal via that changes reference planes. The signal changed layers, so its return current must change planes too, and it needs a path to do that. Without a nearby stitching via, the return current takes a long detour and you get the same loop-area problem described earlier.

Simulate before you fabricate

Signal and power integrity simulation is the highest-leverage step in a high-speed project, and the one most often skipped to save money. This is a false economy that we watch teams pay for repeatedly.

A simulation pass finds impedance mismatches, reflections, crosstalk and resonances while they are still cheap to fix, which is to say while they are still lines on a screen. Once the board is fabricated, the same problems cost you a respin, and a respin costs you the fabrication run, the assembly, the parts, and several weeks of schedule.

The arithmetic is not subtle. A simulation that costs a few hundred dollars routinely prevents a respin that costs several thousand plus a month of delay. We run SI analysis on every controlled-impedance board we design, and it has paid for itself many times over.

A pre-fabrication checklist

• Stack-up agreed with the fabricator, with impedance-matched trace widths confirmed in their process
• No high-speed trace crosses a split or gap in its reference plane
• Differential pairs length-matched, constant-gap, and routed together throughout
• 3W spacing honoured for clocks and other sensitive nets
• Via stubs minimised, back-drilled, or eliminated with blind vias on fast interfaces
• Ground stitching vias placed at every layer transition of a critical signal
• Decoupling capacitors close to the pins they serve, with short, low-inductance connections to the planes
• SI/PI simulation completed and the results actually reviewed
• Design rule check clean, and DFM review passed with the fabricator

Sources and further reading

Primary references for the standards, regulations and figures cited above:

• IPC — Standards for PCB design and assembly — The IPC standards body, including IPC-2221 (generic PCB design) and IPC-A-610 (assembly acceptability).
• IPC-2141: Controlled Impedance Circuit Boards and High-Speed Logic Design — The design standard governing controlled-impedance and high-speed routing.
• Altium — Signal integrity and impedance control resources — Practical reference material on stack-up, differential pairs and via stubs.